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549b54dba8
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LOAD STORE Done.
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2023-11-27 16:43:24 +01:00 |
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4c1983c39d
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Finished store. Boilerplate for load.
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2023-11-22 12:17:24 +01:00 |
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799b8c595a
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ADD, MUL and SOU finished.
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2023-11-22 11:15:55 +01:00 |
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1ce3d7cd2b
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Deleted process logic in cpu. Added mux_bdr to handle first step. Added LC Step 4 to handle Write in memory.
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2023-11-22 10:31:30 +01:00 |
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3958f90873
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Fixed li links that are no longer required. Switch case done after step1_lidi. Fixed di_A being faster.
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2023-11-21 17:40:22 +01:00 |
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8bf6e8aa4d
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Added multiple instruction to avoid data delay. Tested COPY Insruction. memory register linked to li_B.
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2023-11-21 17:14:02 +01:00 |
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87b358b667
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FIXED MEMORY
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2023-11-21 15:50:59 +01:00 |
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c42c0bcf22
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Added instruction COPY, Commenting the idea for COPY in CPU
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2023-11-20 12:13:42 +01:00 |
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884ecdbded
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AFC instruction done. Test Bench for CPU (AFC) done.
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2023-11-20 12:02:40 +01:00 |
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f44b8e02b8
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Base CPU AFC Instruction wiring.
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2023-10-03 16:39:51 +02:00 |
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bc98f10553
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Added pipeline, added cpu declarations.
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2023-10-03 15:31:50 +02:00 |
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e56b0b74d9
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Project Created. Renaming standardisation to snake case
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2023-10-03 14:41:47 +02:00 |
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be238afa0a
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Boilerplate CPU. VHDL files only.
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2023-10-03 14:37:37 +02:00 |
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