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• a14fe32261
  Update README.md main Robin Marin--Muller 2025-01-02 22:51:14 +01:00
• 6647888220
  Update README.md Robin Marin--Muller 2024-12-31 16:02:23 +01:00
• 86d986894c Hot fix for LOAD: using falling edge to respect timing. Yohan Boujon 2023-12-05 20:50:22 +01:00
• 4878e6b2a0 Fixed LOAD. develop Lemonochrome 2023-12-04 21:06:24 +01:00
• 5325019c07 STORE Done. Lemonochrome 2023-12-03 11:53:16 +01:00
• ca7412e7c7 SOUSTRACTION Done. Lemonochrome 2023-12-01 23:10:19 +01:00
• d422136f63 MULTIPLICATION Done. Lemonochrome 2023-12-01 22:44:46 +01:00
• f65b4dfcd0 ADD Done. Lemonochrome 2023-12-01 22:26:39 +01:00
• 51b0f03dbb Gestion alea COPY need to implet others Yohan Boujon 2023-11-30 12:05:14 +01:00
• 77791b514a COPY Done. Lemonochrome 2023-11-29 21:27:57 +01:00
• 909de11c18 Fixed timing problems by re-organizing the pipeline Lemonochrome 2023-11-28 19:34:50 +01:00
• 764a3c61af PC -1 juste PC -1. Yohan Boujon 2023-11-27 18:16:24 +01:00
• 549b54dba8 LOAD STORE Done. Yohan Boujon 2023-11-27 16:43:24 +01:00
• f180a80f12 AFC Done. Lemonochrome 2023-11-27 00:36:16 +01:00
• 962eef8a1f Data flow done. Lemonochrome 2023-11-27 00:08:19 +01:00
• fcfba19562 Process based risc boiler plate Lemonochrome 2023-11-26 23:13:44 +01:00
• c251bc227b Commented component for clarity Lemonochrome 2023-11-26 16:23:26 +01:00
• 4c1983c39d Finished store. Boilerplate for load. Yohan Boujon 2023-11-22 12:17:24 +01:00
• 799b8c595a ADD, MUL and SOU finished. Yohan Boujon 2023-11-22 11:15:55 +01:00
• 1ce3d7cd2b Deleted process logic in cpu. Added mux_bdr to handle first step. Added LC Step 4 to handle Write in memory. Yohan Boujon 2023-11-22 10:31:30 +01:00
• 3958f90873 Fixed li links that are no longer required. Switch case done after step1_lidi. Fixed di_A being faster. Yohan Boujon 2023-11-21 17:40:22 +01:00
• 8bf6e8aa4d Added multiple instruction to avoid data delay. Tested COPY Insruction. memory register linked to li_B. Yohan Boujon 2023-11-21 17:14:02 +01:00
• 87b358b667 FIXED MEMORY Yohan Boujon 2023-11-21 15:50:59 +01:00
• c42c0bcf22 Added instruction COPY, Commenting the idea for COPY in CPU Yohan Boujon 2023-11-20 12:13:42 +01:00
• 884ecdbded AFC instruction done. Test Bench for CPU (AFC) done. Yohan Boujon 2023-11-20 12:02:40 +01:00
• f44b8e02b8 Base CPU AFC Instruction wiring. Yohan Boujon 2023-10-03 16:39:51 +02:00
• bc98f10553 Added pipeline, added cpu declarations. Yohan Boujon 2023-10-03 15:31:50 +02:00
• e56b0b74d9 Project Created. Renaming standardisation to snake case Yohan Boujon 2023-10-03 14:41:47 +02:00
• be238afa0a Boilerplate CPU. VHDL files only. Yohan Boujon 2023-10-03 14:37:37 +02:00
• e6c33c07b5
  Initial commit Lemonochrome 2023-09-29 15:41:38 +02:00