Commit graph

17 commits

Author SHA1 Message Date
Lemonochrome
f65b4dfcd0 ADD Done. 2023-12-01 22:26:39 +01:00
Lemonochrome
77791b514a COPY Done. 2023-11-29 21:27:57 +01:00
Lemonochrome
909de11c18 Fixed timing problems by re-organizing the pipeline 2023-11-28 19:34:50 +01:00
Lemonochrome
f180a80f12 AFC Done. 2023-11-27 00:36:16 +01:00
Lemonochrome
962eef8a1f Data flow done. 2023-11-27 00:08:19 +01:00
Lemonochrome
fcfba19562 Process based risc boiler plate 2023-11-26 23:13:44 +01:00
Lemonochrome
c251bc227b Commented component for clarity 2023-11-26 16:23:26 +01:00
4c1983c39d Finished store. Boilerplate for load. 2023-11-22 12:17:24 +01:00
799b8c595a ADD, MUL and SOU finished. 2023-11-22 11:15:55 +01:00
1ce3d7cd2b Deleted process logic in cpu. Added mux_bdr to handle first step. Added LC Step 4 to handle Write in memory. 2023-11-22 10:31:30 +01:00
3958f90873 Fixed li links that are no longer required. Switch case done after step1_lidi. Fixed di_A being faster. 2023-11-21 17:40:22 +01:00
8bf6e8aa4d Added multiple instruction to avoid data delay. Tested COPY Insruction. memory register linked to li_B. 2023-11-21 17:14:02 +01:00
87b358b667 FIXED MEMORY 2023-11-21 15:50:59 +01:00
884ecdbded AFC instruction done. Test Bench for CPU (AFC) done. 2023-11-20 12:02:40 +01:00
f44b8e02b8 Base CPU AFC Instruction wiring. 2023-10-03 16:39:51 +02:00
bc98f10553 Added pipeline, added cpu declarations. 2023-10-03 15:31:50 +02:00
e56b0b74d9 Project Created. Renaming standardisation to snake case 2023-10-03 14:41:47 +02:00